speedygo55/psu_cyberdeck
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Started Routing PCB

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SpeedyGo55
2026-03-29 22:46:06 +02:00
parent 2e7ca79a9e
commit d04c3c7ec9
45 changed files with 23889 additions and 154 deletions
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87
MaA_psu.kicad_pro
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@@ -39,9 +39,9 @@
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.8,
"height": 1.27,
"width": 2.54
"drill": 0.25,
"height": 0.6096,
"width": 0.6096
},
"silk_line_width": 0.1,
"silk_text_italic": false,
@@ -124,9 +124,9 @@
},
"rules": {
"max_error": 0.005,
"min_clearance": 0.0,
"min_clearance": 0.1,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.5,
"min_copper_edge_clearance": 0.25,
"min_groove_width": 0.0,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
@@ -136,9 +136,9 @@
"min_silk_clearance": 0.0,
"min_text_height": 0.8,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.2,
"min_via_annular_width": 0.1,
"min_through_hole_diameter": 0.25,
"min_track_width": 0.1,
"min_via_annular_width": 0.25,
"min_via_diameter": 0.5,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
@@ -479,7 +479,7 @@
"classes": [
{
"bus_width": 12,
"clearance": 0.2,
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
@@ -490,11 +490,31 @@
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 2147483647,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"track_width": 0.15,
"tuning_profile": "",
"via_diameter": 0.6,
"via_drill": 0.3,
"via_diameter": 0.4,
"via_drill": 0.2,
"wire_width": 6
},
{
"clearance": 0.2,
"name": "3.3v",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 0,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.4,
"tuning_profile": ""
},
{
"clearance": 0.2,
"name": "Power",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 1,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.5,
"tuning_profile": "",
"via_diameter": 0.8,
"via_drill": 0.4
}
],
"meta": {
@@ -502,7 +522,48 @@
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
"netclass_patterns": [
{
"netclass": "Power",
"pattern": "+BATT"
},
{
"netclass": "Power",
"pattern": "-BATT"
},
{
"netclass": "Power",
"pattern": "VSYS"
},
{
"netclass": "Power",
"pattern": "VOUT"
},
{
"netclass": "Power",
"pattern": "*TVS1-A1*"
},
{
"netclass": "Power",
"pattern": "Net-(U2-ACN)"
},
{
"netclass": "Power",
"pattern": "/SW1"
},
{
"netclass": "Power",
"pattern": "Net-(U2-SW2)"
},
{
"netclass": "Default",
"pattern": "+3.3V"
},
{
"netclass": "Default",
"pattern": ""
}
]
},
"pcbnew": {
"last_paths": {